Rating: 3.50
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VLSI design
A symbolic layout is often used in a design process since it simplifies the layout process and can be translated into a composite ... 3.5 To Probe Further VLSI fabrication: • SM Sze, ed., VLSI Technology, 2nd Edition, McGraw-Hill, 1988 .
by M. Michael Vai
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VLSI, technology and design
Spring Meet., Montreal, Canada, May 9-l4, I982; Abstract Number 182. W. Fichtner , “Physics and simulation of small MOS ... JR Brews, W. Fichtner, EH Nicollisn. and SM Sze, “Generalized guide for MOSFET miniaturization," IEEE Electron ...
by Otto G. Folberth, Warren D. Grobman
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Proceedings of the Symposium on Interconnect and Contact Metallization
The polymer passivation during Al and W etching steps turns out to be a key factor to obtain "voids free" Al ... REFERENCES [1] SM Sze, in VLSI Technology, McGrow-Hill, pp.226-227, 1991. [2] CC Tang, DW Wess, Tungsten Etching in CF4 and ...
by Harzara S. Rathore, Electrochemical Society. Electronics Division, Electrochemical Society. Electrodeposition Division
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| Rating: 3.00
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Electronics, power electronics, optoelectronics, microwaves, electromagnetics, and radar
RTF processes can be used for chemical vapor deposition (RTCVD) in the formation of silicides and for epitaxial growth. ... CY Chang and SM Sze, VLSI Technology, New York: McGraw-Hill, 1995. B. Ciciani, Manufacturing Yield of VLSI, ...
by Richard C. Dorf
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Encyclopedia of 20th-century technology
Fabricating transistors by impurity doping of epitaxial single crystals grown from the gas phase was first achieved ... Pearce, CW Crystal growth and wafer preparation, in VLSI Technology, Sze SM, Ed. McGraw-Hill, Singapore, 1985, pp.
by Colin Hempstead, William E. Worthington
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| Rating: 4.00
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Handbook of Semiconductor Silicon Technology
Rapid heating techniques developed initially for implant anneals can be expected to find application in the single wafer or small batch reactor designs for the 1990's. REFERENCES 1. Pearce, CW, Epitaxy, Ch. 2 in VLSI Technology, (SM Sze ...
by William C. O'Mara, Robert B. Herring, Lee Philip Hunt
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| Rating: 5.00
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The electronics handbook
At larger drain biases, the channel resistance can increase with drain bias, even to the point that the current saturates, ... SMSze, pp. 139-210. Wiley, New York. Chen, JY 1990. CMOS Devices and Technology for VLSI.
by Jerry C. Whitaker
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Silicon heterostructure handbook, materials, fabrication, devices, circuits, and applications of SiGe and Si strained-layer epitaxy
Autodoping is minimized so that ultra-shallow and hyperabrupt junctions and alloy profiles can be formed without growth ... DL Harame, DA Herman Jr., and BS Meyerson. IBM J Res Dev 47: 101-139, 2003. 2. SM Sze. VLSI Technology, 2nd ed ...
by John D. Cressler
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SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices
Autodoping is minimized so that ultra-shallow and hyperabrupt junctions and alloy profiles can be formed without growth ... 2. SM Sze. VLSI Technology, 2nd ed. New York: McGraw-Hill, 1988. 3. PM Garone, V. Venkataraman, and JC Sturm.
by John D. Cressler
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| Rating: 2.00
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Microelectronic materials
Once a method is found by which a useful film can be prepared, great trouble is taken to ensure that the deposition process always takes ... RKFERENCES Adams AC 1983 in VLSI Technology ed. SM Sze (New York: McGraw-Hill) p93 Baccarini G, ...
by C. Grovenor
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